Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Error correction based on verification techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Validating PowerPC Microprocessor Custom Memories
IEEE Design & Test
Establishing latch correspondence for embedded circuits of PowerPC microprocessors
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
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We describe techniques for diagnosing errors in formal equivalence checking of RTL and transistor level models of high performance microprocessors at Freescale Semiconductor Inc. We use Symbolic Trajectory based Evalaution (STE) for combinational equivalence checking. STE accurately captures transistor level behaviors. We use simulation based error diagnosis techniques and present a seamless integration of them in our current verification environments.