Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Incremental Design Debugging in a Logic Synthesis Environment
Journal of Electronic Testing: Theory and Applications
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
Journal of Electronic Testing: Theory and Applications
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With increasing chip interconnect distances, open-interconnect is becoming an important defect. The main challenge with open-interconnects stems from its non-deterministic real-life behavior. In this work, we present an efficient diagnostic technique for multiple open-interconnects. The algorithm proceeds in two phases. During the first phase, potential solution sets are identified following a model-free incremental diagnosis methodology. Heuristics are devised to speed up this step and screen the solution space efficiently. In the second phase, a generalized fault simulation scheme enumerates all possible faulty behaviors for each solution from the first phase. We conduct experiments on combinational and full-scan sequential circuits with one, tw0 and three open faults. The results are very encouraging.