Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs

Authors:
Yu-Shen Yang;Andreas Veneris;Paul Thadikaran;Srikanth Venkataraman
Affiliations:
University of Toronto, ON;University of Toronto, ON;Intel Corporation, Hillsboro, OR;Intel Corporation, Hillsboro, OR
Venue:
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Year:
2005

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Abstract

Test model generation is common in the design cycle of custom made high performance low power designs targeted for high volume production. Logic extraction is a key step in test model generation to produce a logic level netlist from the transistor level representation. This is a semi-automated process which is error prone. This paper analyzes typical extraction errors applicable to clocking schemes seen in high-performance designs today. An automated debugging solution for these errors in designs with no state equivalence information is also presented. A suite of experiments on circuits with similar architecture to that found in the industry confirm the fitness and practicality of the solution.