Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Simplifying and Isolating Failure-Inducing Input
IEEE Transactions on Software Engineering
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis
Proceedings of the IEEE International Test Conference
Modeling the unknown! Towards model-independent fault and error diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Debugging Sequential Circuits Using Boolean Satisfiability
MTV '04 Proceedings of the Fifth International Workshop on Microprocessor Test and Verification
Logic design verification via test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Design and manufacturing of present day Multi-Core microprocessors has to overcome major technology obstacles, particularly in the areas of Power and Validation. More specifically, the state of the Art in the area of validation is such that upwards of 30% of the human resources in a modern microprocessor Design Team are dedicated to it. The term Validation Productivity Gap has been introduced to describe exactly these ever increasing resource requirements. Formal Verification techniques offer one of the technological approaches for addressing many aspects of this validation gap. Therefore it is of paramount importance to develop technologies and methodologies for reducing the time it takes to debug and rectify Logic Errors that are detected by Formal Verification Techniques. Such developments would offer a much needed productivity improvement both in pre- and post-Silicon validation activities.