Diagnosis and correction of logic design errors in digital circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation
Proceedings of the IEEE International Test Conference on Test and Design Validity
Modelling the Unmodellable: Algorithmic Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis
Proceedings of the IEEE International Test Conference
Logical Diagnosis Solutions Must Drive Yield Improvement
Proceedings of the IEEE International Test Conference
A fault diagnosis methodology for the UltraSPARC/sup TM/-I microprocessor
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
ErrorTracer: design error diagnosis based on fault simulation techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On correction of multiple design errors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design diagnosis using Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Robust image watermarking scheme based on 3D-DCT
FSKD'09 Proceedings of the 6th international conference on Fuzzy systems and knowledge discovery - Volume 5
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Logical defect diagnosis is a critical yet challenging process in VLSI manufacturing. It involves the identification of the defect spots in a logic IC that fails testing. In the last decade, algorithms for diagnosis have progressed significantly and the results are showing promise for full -scan designs. In this paper, we will first review several classical algorithms such as fault dictionary based analysis and effect cause analysis. Then, we discuss several diagnosis algorithms borrowed from the design debugging techniques. These algorithms do not require a pre-determined fault model, and thus, are more flexible and applicable to ICs in which the defects do not behave like common stuck-at or bridging faults. Finally, we will probe the possibility of extending these algorithms to designs with only partial-scan support.