A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis
Journal of Electronic Testing: Theory and Applications
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
Logic defect diagnosis is to locate the defect spots in a digital IC that fails testing. It is one of the critical steps during the process of manufacturing yield improvement. Automatic defect diagnosis techniques for circuits with single defect have been improved significantly. However, the techniques for multiple defect diagnosis are still inadequate. In this paper, we propose an effective heuristic for diagnosing a full-scan design with multiple defects. Concepts called curable vectors and curable outputs are incorporated. By combing these two measures as a grading criterion, each signal's possibility of being one of the defect spots is calculated with a high accuracy. Experimental results on ISCAS85 benchmark circuits indicate that the proposed method indeed outperforms the conventional heuristics.