Failure Diagnosis of Structured VLSI
IEEE Design & Test
Modeling the Unmodelable: Algorithmic Fault Diagnosis
IEEE Design & Test
Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A Technique for Logic Fault Diagnosis of Interconnect Open Defects
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
An Effective Diagnosis Method to Support Yield Improvement
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Correlation of Logical Failures to a Suspect Process Step
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Design/process learning from electrical test
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
| Hi-index | 0.01 |
Complex SOC's developed in VDSMtechnologies require adequate solutions to diagnose andanalyze yield losses. This paper focuses on the diagnosisof logic circuits embedded in SOCs. The core instrumentleveraged is ATPG used during test vectors generation andanalysis of failures. This work emphasizes the resultsobtained in systematically applying ATPG diagnosis onfailures detected in the manufacturing test floor. Details ondiagnosis flow and ATE data collection are given.Experimental results are provided.