Proceedings of the IEEE International Test Conference
An effective DFM strategy requires accurate process and IP pre-characterization
Proceedings of the 42nd annual Design Automation Conference
Are there economic benefits in DFM?
Proceedings of the 42nd annual Design Automation Conference
Value-Added Defect Testing Techniques
IEEE Design & Test
Precise failure localization using automated layout analysis of diagnosis candidates
Proceedings of the 45th annual Design Automation Conference
Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
DREAMS: DFM rule EvAluation using manufactured silicon
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Design for manufacturability (DFM) is inevitable because of the formidable challenges encountered in nano-scale integrated circuit (IC) manufacturing. Unfortunately, it is difficult for designers to understand the cost-benefit tradeoff when tuning their design through DFM to achieve better manufacturability. This work attempts to assist the designer in this aspect by providing a methodology (called RADAR --- Rule Assessment of Defect-Affected Regions) which uses failing-IC diagnosis results to systematically evaluate the effectiveness of DFM rules. RADAR is applied to the fail data from a 90nm Nvidia graphics processing unit (GPU) to demonstrate its viability. Specifically, evaluation of the via-enclosure rules revealed that they are much more needed in metal layers 3--6 than the remaining layers.