Trace Compaction using SAT-based Reachability Analysis

Authors:
Sean Safarpour;Andreas Veneris;Hratch Mangassarian
Affiliations:
Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada. sean@eecg;Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada. veneris@e;Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada. hratch@ee
Venue:
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Year:
2007

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Abstract

In today's designs, when functional verification fails, engineers perform debugging using the provided error traces. Reducing the length of error traces can help the debugging task by decreasing the number of variables and clock cycles that must be considered. We propose a novel trace length compaction approach based on SAT-based reachability analysis. We develop procedures and algorithms using pre-image computation to efficiently traverse the state space and reduce the trace lengths. We further introduce a data structure used to store the visited states which is critical to the performance of the proposed approach. Experiments demonstrate the effectiveness of the reachability approach as approximately 75% of the traces are reduced by one or two orders of magnitudes.