Built-in self at-speed delay binning and calibration mechanism in wireless test platform
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
An on-chip delay measurement technique using signature registers for small-delay defect detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Delay testing has become a major issue for manufacturing advanced Systems on a Chip. Automatic Test Equipment and scan techniques are usually applied in delay testing. However, the circuits under test have many circuit paths and dependent input patterns; it is hard to measure delay times accurately, especially when debugging small delay defects. We propose a Built-In Delay Measurement (BIDM) circuit that is modified from Vernier Delay Lines. All digitally designed BIDMs with small area overhead can be easily embedded within testing circuits. BIDMs can be used to record the data propagation delay times within circuit path segments, for delay testing, diagnosis, and calibration requirements internal to the chip. Our BIDM was implemented in a 32bit error correction circuit by a chip using TSMC 0.18u technology. The instruments measured results showing that the BIDM chip correctly reported the CUT segment path delay times. The chip measurement results were a 95.83% match to the postlayout SPICE simulation values. This BIDM makes it possible to debug small delay defects in chips.