A BIST Approach for Very Deep Sub-Micron (VDSM) Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Testing resistive opens and bridging faults through pulse propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Recent empirical and simulation studies show that adding at-speed testing to the test suite helps in detecting defective ICs missed by slow-speed and I/sub DDQ/ testing. At-speed testing attempts to detect ICs with defects, like bridges and opens, which cause faulty dynamic logic behavior. Path delay tests and transition tests are two popular tests used during at-speed testing. We show that these tests often fail to detect many bridges and opens which cause faulty dynamic behavior. Computing at speed tests is therefore fundamentally different from computing delay tests for parametric testing and new techniques need to be developed.