Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits

Authors:
Kai-Chiang Wu;Diana Marculescu;Ming-Chao Lee;Shih-Chieh Chang
Affiliations:
Carnegie Mellon University, Pittsburgh, PA, USA;Carnegie Mellon University, Pittsburgh, PA, USA;National Tsing Hua University, Hsinchu, Taiwan Roc;National Tsing Hua University, Hsinchu, Taiwan Roc
Venue:
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Year:
2011

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Abstract

Device aging, which causes significant loss on circuit performance and lifetime, has been a main factor in reliability degradation of nanoscale designs. Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of supply voltage, necessitate an aging-aware analysis and optimization flow in the early design stages. Since PMOS sleep transistors in power-gated circuits suffer from static NBTI during active mode and age very rapidly, the aging of power-gated circuits should be explicitly addressed. In this paper, for power-gated circuits, we present a novel methodology for analyzing and mitigating NBTI-induced performance degradation. Aging effects on both logic networks and sleep transistors are jointly considered for accurate analysis. By introducing 25% redundant sleep transistors with reverse body bias applied, the proposed methodology can significantly mitigate the long-term performance degradation and thus extend the circuit lifetime by 3X.