Critical-reliability path identification and delay analysis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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In this paper, a computer-aided design system for CMOS VLSI circuit hot-carrier reliability estimation and redesign is presented. The system first simulates a circuit to determine the critical transistors that are most susceptible to hot-carrier effects (HCEs). It then estimates the impact of HCE on circuit performance and employs a combination of design modification strategies to eliminate HCE-induced performance degradation. Two criteria are used to evaluate HCE degradation. The first criterion is the estimation of local damage in each transistor, which indicates the possibility of failure of individual devices. The second criterion is the global degradation of the circuit, namely the increase of delay in digital circuits. If either criterion exceeds a user-specified limit, several alternative circuit redesign strategies can be chosen by the user from a suggested menu. Based on this choice, the system will automatically redesign the critical parts of the circuit to improve circuit performance. The advantages and disadvantages of these alternative redesign strategies are also compared