Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
An efficient method to identify critical gates under circuit aging
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Self-calibrating Online Wearout Detection
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Online circuit reliability monitoring
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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The increasing significance of Negative Bias Temperature Instability (NBTI) induced device-reliability degradation presents a compelling reason to perform efficient circuit-level reliability tracking. We propose a novel collaborative monitoring frame-work to track circuit level performance degradation caused specifically by NBTI. We use heterogeneous on-chip sensors to measure environmental and stress parameters and a macro-model to map the device-level degradation information into circuit-level reliability estimates. The macro-model is built using curve-fitted data and provides a practical upper bound of the path-delay-degradation to expect under a given set of dynamic parameters which includes operating conditions, process and stress parameters. Through usage of on-chip sensing resources we minimize the need for extensive circuit-specific analyses and also, the pessimism caused by assuming worst-case operating corners. We validate our approach on ISCAS-85 benchmarks and observe excellent correlation (0.99) between worst-case SPICE observed and model-predicted path-delay degradation.