The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A unified approach for timing verification and delay fault testing
A unified approach for timing verification and delay fault testing
Accuracy Requirements in At-Speed Functional Test
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
System performance management for the S/390 parallel enterprise server G5
IBM Journal of Research and Development
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 0.00 |
The correlation between the delays of varioustypes of paths on an Integrated Circuit (IC) is studied.The correlation between delays of differentcritical paths is found to be low. An estimate ismade of the correlation between the maximum frequencyat which the IC can operate and the delayof some specific path on it. This correlationimproves as the number of critical and near criticalpath increases, but will never be perfect.