Multiple Scan Chain Design for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Power Driven Chaining of Flip-Flops in Scan Architectures
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Efficient techniques for transition testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Routing-aware scan chain ordering
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
IEEE Design & Test
Layout-aware scan chain synthesis for improved path delay fault coverage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan-chain partition for high test-data compressibility and low shift power under routing constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT-based generation of compressed skewed-load tests for transition delay faults
Microprocessors & Microsystems
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Launch-off-shift (LOS) is a popular delay test technique for scan-based designs. However, it is usually not possible to achieve good delay fault coverage in LOS test due to conflicts in test vectors. In this article, we propose a layout-based scan chain ordering method to improve fault coverage for LOS test with limited routing overhead. A fast and effective algorithm is used to eliminate conflicts in test vectors while at the same time restrict the extra scan chain routing. This approach provides many advantages. (1) The proposed method can improve delay fault coverage for LOS test. (2) With layout information taken into account, the routing penalty is limited, and thus the impact on circuit performance will not be significant. Experimental results show that the proposed LOS test method achieves about the same level of delay fault coverage as enhanced scan does, while the average scan chain wire length is about 2.2 times of the shortest scan chain.