On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains

• Venue: ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
• Year: 2002

The use of multiple scan chains for a scan design reduces the test application time by reducing the number of clock cycles required for a scan-in/scan-out operation. In this work, we show that the use of multiple scan chains also increases the fault coverage achievable for delay faults, requiring two-pattern tests, under the scan-shift test application scheme. Under this scheme, the first pattern of a two-pattern test is scanned in, and the second pattern is obtained by shifting the scan chain once more. We also demonstrate that the specific way in which scan flip-flops are partitioned into scan chains affects the delay fault coverage. This is true even if the order of the flip-flops in the scan chains remains the same. To demonstrate this point, we describe a procedure that partitions scan flip-flops into scan chains so as to maximize the coverage of transition faults.