ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A new scan architecture, called enhanced scan forest, is proposed to detect path delay faults and reduce test stimulus data volume, test response data volume, and test application time. The enhanced scan forest architecture groups scan flipflops together, where all scan flip-flops in the same group are assigned the same value for all test vectors. All scan flipflops in the same group share the same hold latch, and the enhanced scan forest architecture makes the circuit work in the same way as a conventional enhanced scan design. The area overhead of the proposed enhanced scan forest is greatly reduced compared to that for enhanced scan design. A lowarea- overhead zero-aliasing test response compactor is designed for path delay faults. Experimental results for the ISCAS benchmark circuits are presented to demonstrate the effectiveness of the proposed method.