Analysis of timing failures due to random AC defects in VLSI modules
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Quality level and fault coverage for multichip modules
DAC '83 Proceedings of the 20th Design Automation Conference
Statistical techniques of timing verification
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
An Experimental Delay Test Generator for LSI Logic
IEEE Transactions on Computers
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
Timing analysis of computer hardware
IBM Journal of Research and Development
Design for Testability in Nanometer Technologies; Searching for Quality
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Low Voltage Test in Place of Fast Clock in DDSI Delay Test
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 0.00 |
This paper presents a quantitative delay fault coverage model to provide a figure of merit for delay testing. System sensitivity of a path to a delay fault along that path and the effectiveness of a delay test are described in terms of the propagation delay of the path under test and the delay defect size. A new statistical delay fault coverage (SDFC) model is established. A new defect level model is also proposed as a function of the yield of a manufacturing process and the new statistical delay fault coverage.