A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a two-phase test generation method to generate patterns targeting maximal path delay caused by multiple crosstalk effects. A timing analysis method based on transition map is proposed to manage the timing information of aggressor lines and victim lines in the first phase, followed by an ordinary ATPG engine with a few alterations in the second phase. This two-phase method avoids complex timing processing in ATPG algorithm. Using transition map instead of timing window in timing analysis, our method can more efficiently calculate the accumulative crosstalk-induced delay and find the sub-paths which cause maximal coupling effects. We can trade off accuracy and efficiency by controlling the size of timescale used in transition map, which makes this approach highly scalable.