A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AC-plus scan methodology for small delay testing and characterization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Scan based timing comparison tests offer a potential solution to the problem of small delay detection in aggressive nanometer technologies. However, such tests require that circuit delays be unambiguously captured in the scan chains using multiple fast clocks. To ensure this, only those signals that are known to be hazard free at capture are analysed for timing information from the scan-out data. In this paper we present the first systematic ATPG driven approach for generating high coverage output hazard free TDF tests for scan delay testing. Results indicate that acceptable coverage can be achieved, no worse than about 10% below the unconstrained TDF coverage for both LOS and LOC tests, even in the presence of significant process variations.