System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Efficient EVM testing of wireless OFDM transceivers using null carriers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RF on-chip test by reconfiguration technique
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
System-level specification testing of wireless transceivers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Production testing of wireless transmit systems incurs high test cost primarily due to the need for using lengthy bit-sequences for testing critical specifications, such as adjacent-channel-power ratio (ACPR) and error-vector-magnitude (EVM). Given the production test sequence for measuring multiple specifications of a transmitter-under-test, switching from one test hardware setup to the next, impacts test time. In this paper, anew test methodology for wireless transmitters is demonstrated, in which a single stimulus is used to test multiple frequency-domain and modulation-domain transmitter specifications in a significantly short test time. In the proposed test method, a multi-tone stimulus is applied at the baseband of the transmitter-under-test; the corresponding spectral test response at the RF output of the transmitter is analyzed for predicting the transmitter specifications using an alternate testing framework. Pass/fail decisions are made using the predicted specification values. Experimental data for a 1.575 GHz digital-IF transmitter prototype is presented.