Reliability of majority voting based VLSI fault-tolerant circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Multifrequency Analysis of Faults in Analog Circuits
IEEE Design & Test
Defect-oriented testing of mixed-signal ICs: some industrial experience
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Signature Test Framework for Rapid Production Testing of RF Circuits
Proceedings of the conference on Design, automation and test in Europe
A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Mixed Loopback BiST for RF Digital Transceivers
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
An Ultra-Fast, On-Chip BiST for RF Low Noise Amplifiers
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing)
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing)
Testing RF Components with Supply Current Signatures
ATS '07 Proceedings of the 16th Asian Test Symposium
Prediction of analog performance parameters using fast transient testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-voltage improved accuracy Gaussian function generator with fourth-order approximation
Microelectronics Journal
Testing RF circuits with true non-intrusive built-in sensors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Wide Dynamic Range CMOS Amplifier Design for RF Signal Power Detection via Electro-Thermal Coupling
Journal of Electronic Testing: Theory and Applications
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This paper presents an efficient, low-cost, built-in test (BIT) circuit for radio frequency differential low noise amplifiers (DLNAs). The BIT circuit detects amplitude alterations at the outputs of the DLNA, due to parametric or catastrophic faults, and provides a single digital Pass/Fail indication signal. A triple modular redundancy approach has been adopted for the BIT circuit design to avoid possible yield loss in case of a malfunctioning test circuitry. The technique has been evaluated on a typical CMOS RF DLNA and simulation results are presented.