A Design Diversity Metric and Analysis of Redundant Systems
IEEE Transactions on Computers
14.2 Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Design Diversity Metric and Reliability Analysis for Redundant Systems
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Self-Checking Voter for High Speed TMR Systems
Journal of Electronic Testing: Theory and Applications
Majority-based reversible logic gates
Theoretical Computer Science
Proceedings of the 1st workshop on Architectural and system support for improving software dependability
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A built-in-test circuit for RF differential low noise amplifiers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
MEMS dynamic optically reconfigurable gate array usable under a space radiation environment
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Triple module redundancy of a laser array driver circuit for optically reconfigurable gate arrays
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
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The effect of compensating module faults on the reliability of majority voting based VLSI fault-tolerant circuits is investigated using a fault injection simulation method. This simulation method facilitates consideration of multiple faults in the replicated circuit modules as well as the majority voting circuits to account for the fact that, in VLSI implementations, the majority voting circuits are constructed from components of the same reliability as those used to construct the circuit modules. From the fault injection simulation, a survivability distribution is obtained which, when combined with an area overhead expression, leads to a more accurate reliability model for majority voting based VLSI fault-tolerant circuits. The new model is extended to facilitate the calculation of reliability of fault-tolerant circuits which have sustained faults but continue to operate properly. Analysis of the reliability model indicates that, for some circuits, the reliability obtained with majority voting techniques is significantly greater than predicted by any previous model.