An Ultra-Fast, On-Chip BiST for RF Low Noise Amplifiers
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
IEEE Communications Magazine
A low-cost test solution for wireless phone RFICs
IEEE Communications Magazine
Signature analysis for analog and mixed-signal circuit test response compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Self-Calibration of Output Match and Reverse Isolation in LNAs Based Switchable Resistor
Journal of Electronic Testing: Theory and Applications
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RFIC reliability is fast becoming a major bottleneck in the yield and performance of modern IC systems, as process complexity and levels of integration continually increase. Due to high frequencies involved, testing these chips is both complicated and expensive. While the areas of Automated testing and Self-test have received significant attention over the past few years, no formal framework of fault-models or sensitivity-models exists in the RF domain. This paper describes a Sensitivity Analysis methodology as a first step towards such a framework. It is applied towards a Low Noise Amplifier, and a case-study application is discussed by using design and experimental results of an adaptive LNA designed in the IBM6RF 0.25 μm CMOS process.