Optimal ordering of analog integrated circuit tests to minimize test time
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Multifrequency Analysis of Faults in Analog Circuits
IEEE Design & Test
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs
IEEE Design & Test
Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Diagnosis of Failing Component in RF Receivers through Adaptive Full-Path Measurements
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Delayed-RF Based Test Development for FM Transceivers Using Signature Analysis
ITC '04 Proceedings of the International Test Conference on International Test Conference
A low-cost test solution for wireless phone RFICs
IEEE Communications Magazine
Enhanced error vector magnitude (EVM) measurements for testing WLAN transceivers
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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The test cost of RF systems is an increasing percentage of the overall system cost. This trend is mainly due to the traditional RF testing schemes based on the full measurement of specifications over a wide range of input conditions. In this paper, we present a test development methodology for RF circuits based on a novel parametric fault definition. We target deviations in physical circuit parameters, such as a resistance or the width of a transistor. However, we consider a circuit faulty only if it violates a specification. Our test development method aims at reducing not only the number of measurements, but also the overall test hardware cost by incorporating the relative set-up cost of each measurement into our selection criteria. Experimental results on a low-noise amplifier (LNA) circuit show that our test development technique reduces the overall test time (49%-67%) as well as the number of required measurement set-ups (17%-33%) considerably. By defining the target faults based on specification violations, our technique also provides high confidence in the test quality.