A Signature Test Framework for Rapid Production Testing of RF Circuits
Proceedings of the conference on Design, automation and test in Europe
A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
An Ultra-Fast, On-Chip BiST for RF Low Noise Amplifiers
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Journal of Electronic Testing: Theory and Applications
Built-In Test of RF Components Using Mapped Feature Extraction Sensors
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Diagnosis of Failing Component in RF Receivers through Adaptive Full-Path Measurements
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On-Chip Testing Techniques for RF Wireless Transceivers
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe
Defect Filter for Alternate RF Test
ETS '09 Proceedings of the 2009 European Test Symposium
Efficient EVM testing of wireless OFDM transceivers using null carriers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Communications Magazine
A low-cost test solution for wireless phone RFICs
IEEE Communications Magazine
Prediction of analog performance parameters using fast transient testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel and low-cost methodology for testing embedded Low Noise Amplifiers (LNAs). It is based on the detection and analysis of the response envelope of the Device Under Test (DUT) to a two-tone input signal. The envelope signal is processed to obtain a digital signature sensitive to key specifications of the DUT. An optimized regression model based on ensemble learning is used to relate the digital signatures to the target specifications. A new Figure of Merit (FOM) is proposed to evaluate the prediction accuracy of the statistical model, and a demonstrator has been developed to prove the feasibility of the approach. This demonstrator features a 2.445 GHz low-power LNA and a simple envelope detector, and has been developed in a 90 nm CMOS technology. Post-layout simulations are provided to verify the functionality of the proposed test technique.