A new built-in self-test approach for digital-to-analog and analog-to-digital converters
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Proceedings of the IEEE International Test Conference
A BIST Scheme for an SNR Test of a Sigma-Delta ADC
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Efficient and accurate testing of analog-to-digital converters using oscillation-test method
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Built-in self-test methodology for A/D converters
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Towards an ADC BIST Scheme Using the Histogram Test Technique
ETW '00 Proceedings of the IEEE European Test Workshop
Diagnostic analysis of static errors in multi-step analog to digital converters
Proceedings of the conference on Design, automation and test in Europe
Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures
Journal of Electronic Testing: Theory and Applications
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This paper reports a new built-in self-test scheme for analog and mixed-signal devices based on die-level process monitoring. The objective of this test is not to replace traditional specification-based tests, but to provide a reliable method for early identification of excessive process parameter variations in production tests that allows quickly discarding of the faulty circuits. Additionally, the possibility of on-chip process deviation monitoring provides valuable information, which is used to guide the test and to allow the estimation of selected performance figures. The information obtained through guiding and monitoring process variations is re-used and supplement the circuit calibration.