DSP-Based Testing of Analog and Mixed-Signal Circuits
DSP-Based Testing of Analog and Mixed-Signal Circuits
Analog Signal Generation for Built-in-Self-Test of Mixed-Signal Integrated Circuits
Analog Signal Generation for Built-in-Self-Test of Mixed-Signal Integrated Circuits
A Signature Analyzer for Analog and Mixed-signal Circuits
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Proceedings of the IEEE International Test Conference
A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Efficient and accurate testing of analog-to-digital converters using oscillation-test method
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Built-in self-test methodology for A/D converters
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Hardware Resource Minimization for Histogram-Based ADC BIST
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST
Journal of Electronic Testing: Theory and Applications
An efficient linearity test for on-chip high speed ADC and DAC using loop-back
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST
Journal of Electronic Testing: Theory and Applications
Combined Self-Test of Analog Portion and ADCs in Integrated Mixed-Signal Circuits
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Digital Test Method for Embedded Converters with Unknown-Phase Harmonics
Journal of Electronic Testing: Theory and Applications
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This paper discusses the viability of a BIST implementation for the sinusoidal histogram technique classically used for ADC testing. An original approach based on (i) approximations to estimate the ADC parameters, (ii) decomposition of the global test in a code-after-code test procedure and (iii) piece-wise approximation to compute the ideal histogram is developed. These three features allow a significant reduction of the required operative resources as well as the required memory resources dedicated to the storage of both experimental and reference data.