An efficient linearity test for on-chip high speed ADC and DAC using loop-back

Authors:
Ji Hwan (Paul) Chun;Hak-soo Yu;Jacob A. Abraham
Affiliations:
The University of Texas at Austin, Austin, TX;The University of Texas at Austin, Austin, TX;The University of Texas at Austin, Austin, TX
Venue:
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Year:
2004

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Abstract

Our method extracts the linearity of on-chip high speed data converters with minimum area overhead. With a loop-back setup in the presence of noise, differential nonlinearities (DNLs) and integral nonlinearities (INLs) of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) can be extracted by the proposed method. Our approach exploits the fact that the loop-back output distribution due to noise is distorted by nonlinearities of the ADC, but not by those of the DAC. We first fully characterize the ADC in the loop-back system, exclusive of the DAC. Then, the DAC is characterized using the extracted nonlinearities of the ADC. Numerical simulation shows a maximum error of less than ±0.1 LSB for the ADC and the DAC.