A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Implementation of a linear histogram BIST for ADCs
Proceedings of the conference on Design, automation and test in Europe
Analog and Mixed-Signal Benchmark Circuits-First Release
Proceedings of the IEEE International Test Conference
Proceedings of the IEEE International Test Conference
HABIST: Histogram-Based Analog Built-In Self-Test
Proceedings of the IEEE International Test Conference
Testing mixed-signal cores: practical oscillation-based test in an analog macrocell
ATS '00 Proceedings of the 9th Asian Test Symposium
Towards an ADC BIST Scheme Using the Histogram Test Technique
ETW '00 Proceedings of the IEEE European Test Workshop
Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Hardware Resource Minimization for Histogram-Based ADC BIST
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
IEICE - Transactions on Information and Systems
Low-Cost IP Core Test Using Tri-Template-Based Codes
IEICE - Transactions on Information and Systems
Crossroads for mixed-signal chips
IEEE Spectrum
Testing analog and mixed-signal integrated circuits using oscillation-test method
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Testing is a critical stage in integrated circuits production in order to guarantee reliability. The complexity and high integration level of mixed-signal ICs has put forward new challenges to circuit testing. This paper describes an oscillation-based combined self-test strategy for the analog portion and analog-to-digital converters (ADCs) in integrated mixed-signal circuits. In test mode, the analog portion under test is reconfigured into an oscillator, generating periodic signals as the test stimulus of ADC. By analyzing the A/D conversion results, a histogram test of ADC can be performed, and the oscillation frequency as well as amplitude can be checked, and in this way the oscillation test of the analog portion is realized simultaneously. For an analog benchmark circuit combined with an ADC, triangle oscillation and sinusoid oscillation schemes are both given to test their faults. Experimental results show that fault coverage of the analog portion is 92.2% and 94.3% in the two schemes respectively, and faults in the ADC can also be tested.