Built-in self-test methodology for A/D converters

Authors:
R. de Vries;T. Zwemstra;E. M. J. G. Bruls;P. P. L. Regtien
Affiliations:
Philips Research Lab., Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands;Philips Semiconductors, Gerstweg 2, 6534 AE Nijmegen, The Netherlands;Philips Research Lab., Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands;University of Twente, P.O. Box 217, 750O AE Enschede, The Netherlands
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

Citing 4
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Abstract

A (partial) Built-in Self-Test (BIST) methodology is proposed for analog to digital (A/D) converters. In this methodology the number of bits of the A/D converter that needs to be monitored externally in a test is reduced. This reduction depends, among other things, on the frequency of the applied test signal. At low test signal frequencies only the least significant bit (LSB) needs to be monitored and a "full" BIST becomes feasible. An analysis is made of the trade-off between the size of the on-chip test circuitry and the accuracy of this BIST technique.