A new built-in self-test approach for digital-to-analog and analog-to-digital converters
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Proceedings of the IEEE International Test Conference
A BIST Scheme for an SNR Test of a Sigma-Delta ADC
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
DfT and on-line test of high-performance data converters: a practical case
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Built-in self-test methodology for A/D converters
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Proceedings of the 42nd annual Design Automation Conference
| Hi-index | 0.01 |
Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The operational principle of both strategies relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong precision requirements, by a resistive network. The main differences between both strategies relate to the way the output response is evaluated. In the BIST#1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BIST#2 strategy, only digital outputs are available and they are compared with fault-free values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism.