A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs
Journal of Electronic Testing: Theory and Applications
BIST for D/A and A/D Converters
IEEE Design & Test
Built-in self-test methodology for A/D converters
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Testing and Characterization of the One-Bit First-Order Delta-Sigma
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A design-for-digital-testability circuit structure for Σ-Δ modulators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A decorrelating design-for-digital-testability scheme for Σ-Δ modulators
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Automatic linearity and frequency response tests with built-in pattern generator and analyzer
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On chip testing data converters using static parameters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper demonstrates a digitally testable second-order Σ - Δ modulator. The modulator under test (MUT) employs the decorrelating design-for-digital-testability (D3T) scheme to provide two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of the (D3T) modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a Σ - Δ modulated bit-stream as its test stimulus. By repetitively inputting the DCCs with the same Σ - Δ modulated bit-stream but with different delays, the DCCs incorporates with the integrator to generate the analog stimulus in the digital test mode. The analog stimulus is analogous to the result of filtering the bit-stream with a two-nonzero-term FIR decorrelating term. Consequently, the D3T MUT suffers less from the undesired shaped noise of the digital stimuli, and achieves better digital test accuracy. Measurement results show that the digital tests present a peak signal-to-noise-and-distortion ratio (SNDR) of 80.1 dB at an oversampling ratio of 128. The SNDR results of the digital tests differ from their conventional analog counterparts by no more than 2 dB except for the -3.2 dBFS test. The analog hardware overhead of the D3T MUT only consists of 13 switches.