DATE '00 Proceedings of the conference on Design, automation and test in Europe
A sigma-delta modulation based BIST scheme for mixed-signal circuits
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Efficient and accurate testing of analog-to-digital converters using oscillation-test method
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Ultra Low Cost Analog BIST Using Spectral Analysis
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Self Calibrated ADC BIST Methodology
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
On chip testing data converters using static parameters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing analog and mixed-signal integrated circuits using oscillation-test method
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Built-in-Self-Test Σ-Δ ADC Prototype
Journal of Electronic Testing: Theory and Applications
A decorrelating design-for-digital-testability scheme for Σ-Δ modulators
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low-cost digital detection of parametric faults in cascaded ΣΔ modulators
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A low-power digitally-programmable variable gain amplifier in 65 nm CMOS
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A digitally testable Σ-Δ modulator using the decorrelating design-for-digital-testability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Output Response Analyzer Circuit for ADC Built-in Self-Test
Journal of Electronic Testing: Theory and Applications
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A design-for-digital-testability (DfDT) switched-capacitor circuit structure for testing Σ-Δ modulators with digital stimuli is presented to reduce the overall testing cost. In the test mode, the DfDT circuits are reconfigured as a one-bit digital-to-charge converter to accept a repetitively applied Σ-Δ modulated bit-stream as its stimulus. The single-bit characteristic ensures that the generated stimulus is nonlinearity free. In addition, the proposed DfDT structure reuses most of the analog components in the test mode and keeps the same loads for the operational amplifiers as if they were in the normal mode. It thereby achieves many advantages including lower cost, higher fault coverage, higher measurement accuracy, and the capability of performing at-speed tests. A second-order Σ-Δ modulator was designed and fabricated to demonstrate the effectiveness of the DfDT structure. Our experimental results show that the digital test is able to measure a harmonic distortion lower than -106 dBFS. Meanwhile, the dynamic range measured with the digital stimulus is as high as 84.4 dB at an over-sampling ratio of 128. The proposed DfDT scheme can be easily applied to other types of Σ-Δ modulators, making them also digitally testable.