Implementation of a linear histogram BIST for ADCs
Proceedings of the conference on Design, automation and test in Europe
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Proceedings of the IEEE International Test Conference
Test Metrics for Analog Parametric Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Experimental Validation of a Fully Digital BISTfor Cascaded \Sigma \Delta Modulators
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
A design-for-digital-testability circuit structure for Σ-Δ modulators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The test of ΣΔ modulators is cumbersome due to the high performance that they reach. Moreover, technology scaling trends raise serious doubts on the intradie repeatability of devices. An increase of variability will lead to an increase in parametric faults that are difficult to detect. In this paper, a design-oriented testing approach is proposed to perform a simple and low-cost detection of variations in important design variables of cascaded ΣΔ modulators. The digital tests could be integrated in a production test flow to improve fault coverage and bring data for silicon debug. A study is presented to tailor signature generation, with test-time minimization in mind, as a function of the desired measurement precision. The developments are supported by experimental results that validate the proposal.