A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs
Journal of Electronic Testing: Theory and Applications
DSP-Based Testing of Analog and Mixed-Signal Circuits
DSP-Based Testing of Analog and Mixed-Signal Circuits
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST
Journal of Electronic Testing: Theory and Applications
Computing Functions cos/sup -1/ and sin/sup -1/ Using CORDIC
IEEE Transactions on Computers
CORDIC-based computation of arccos and arcsin
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors
Journal of Electronic Testing: Theory and Applications
Low Cost BIST for Static and Dynamic Testing of ADCs
Journal of Electronic Testing: Theory and Applications
Histogram Based Testing Strategy for ADC
ATS '06 Proceedings of the 15th Asian Test Symposium
A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters
Journal of Electronic Testing: Theory and Applications
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST
Journal of Electronic Testing: Theory and Applications
A design-for-digital-testability circuit structure for Σ-Δ modulators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Built-in-Self-Test Σ-Δ ADC Prototype
Journal of Electronic Testing: Theory and Applications
On chip testing data converters using static parameters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, a structure of the output response analyzer (ORA) circuit for analog-to-digital converters (ADCs) built-in self-test (BIST) is presented. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to estimate the degradation of signal-to-noise ratio (SNR) value. The appropriate approximations of the testing parameters reduce difficulties in designing the complete ORA circuit. In addition, the feature of reusable hardware in the calculation of sine-wave reference histograms and the computing capability of ADCs' parameters further improves the ORA design. This design is compact and easily to be adjusted by different setting. The developed ORA circuits are synthesized in a 0.18-μm technology to analyze the outputs of an 8-bit ADC to verify the designs.