A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Mixed-signal BIST using correlation and reconfigurable hardware (poster paper)
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Implementation of a linear histogram BIST for ADCs
Proceedings of the conference on Design, automation and test in Europe
Statistical Digital Signal Processing and Modeling
Statistical Digital Signal Processing and Modeling
A Signature Analyzer for Analog and Mixed-signal Circuits
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Efficient and accurate testing of analog-to-digital converters using oscillation-test method
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Noise Generator for Analog-to-Digital Converter Testing
Proceedings of the 15th symposium on Integrated circuits and systems design
Hardware Resource Minimization for Histogram-Based ADC BIST
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Step Response Based Mixed-Signal BIST Approach
DFT '01 Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Estimating the Integral Non-Linearity of Ad-Converters via the Frequency Domain
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Built-in-Self-Test Σ-Δ ADC Prototype
Journal of Electronic Testing: Theory and Applications
A dynamic ADC test processor for built-in-self-test of ADCs
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
An Output Response Analyzer Circuit for ADC Built-in Self-Test
Journal of Electronic Testing: Theory and Applications
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This paper presents a low cost test method for the static and dynamic characterization of analog-to-digital converters. The method is suitable for implementation in a SoC environment, as a built-in self test (BIST) solution. In the proposed approach, noise is used as the test signal. Theory of operation and practical results demonstrating the effectiveness of the method for INL, DNL, THD and SINAD characterization are presented. The BIST surface overhead caused by the noise generator is only 7.4% of the ADC total area. The reduced number of data samples required allows a reduction of about 7.5脳 in test time, in comparison to the histogram method.