DATE '00 Proceedings of the conference on Design, automation and test in Europe
Implementation of a linear histogram BIST for ADCs
Proceedings of the conference on Design, automation and test in Europe
Efficient and accurate testing of analog-to-digital converters using oscillation-test method
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Ultra Low Cost Analog BIST Using Spectral Analysis
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Self Calibrated ADC BIST Methodology
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors
Journal of Electronic Testing: Theory and Applications
An On-Chip Spectrum Analyzer for Analog Built-In Testing
Journal of Electronic Testing: Theory and Applications
Low Cost BIST for Static and Dynamic Testing of ADCs
Journal of Electronic Testing: Theory and Applications
CONTROLLED SINE WAVE FITTING FOR ADC TEST
ITC '04 Proceedings of the International Test Conference on International Test Conference
A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters
Journal of Electronic Testing: Theory and Applications
A BIST Scheme for SNDR Testing of ΣΔ ADCs Using Sine-Wave Fitting
Journal of Electronic Testing: Theory and Applications
A design-for-digital-testability circuit structure for Σ-Δ modulators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A decorrelating design-for-digital-testability scheme for Σ-Δ modulators
IEEE Transactions on Circuits and Systems Part I: Regular Papers
On chip testing data converters using static parameters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Output Response Analyzer Circuit for ADC Built-in Self-Test
Journal of Electronic Testing: Theory and Applications
A Reconfiguration Method to Improve the Yield of Bandwidth-Limited Pipelined ADCs
International Journal of Measurement Technologies and Instrumentation Engineering
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This paper presents a built-in-self-test (BIST) Σ-Δ ADC prototype. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order design-for-digital-testability Σ-Δ modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the SNDR difference between conventional FFT analysis and the proposed BIST design of the standard − 6 dBFS, 1 KHz tone test is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.