A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters
Journal of Electronic Testing: Theory and Applications
Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation
Journal of Electronic Testing: Theory and Applications
A Built-in-Self-Test Σ-Δ ADC Prototype
Journal of Electronic Testing: Theory and Applications
BIST/Digital-Compatible Testing of RF Devices Using Distortion Model Fitting
Journal of Electronic Testing: Theory and Applications
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In this paper we introduce a novel procedure for testing the dynamic parameters of Analog to Digital Converters (ADC). The test response of the ADC is compared with a reference signal which is supplied by the tester. The evaluation of the parameters is done in time domain in real time. The method has the potential for being very advantageously implemented as a Built-In Self-Test (BIST) into a mixed signal circuit. Goal of the development was to reduce test time significantly compared to the state of the art methods. With regard to a BIST solution another essential requirement was to keep the complexity of the test circuitry as low as possible, to get only a small additional chip area for realization. Both goals were reached successfully. The test time was reduced to a quarter and the number of gates needed is smaller than 6,700. In a first step the algorithm was modeled at system level and the correctness of the procedure was proven by simulations. To get a reliable estimation of the number of gates necessary for an implementation, the optimized model was redesigned in VHDL. Based on the VHDL code a Field Programmable Gate Array (FPGA) was configured which led to the gate count estimation. Measurements on a Teradyne J750 tester showed that the accuracy of the method is equivalent to FFT based methods.