A sigma-delta modulation based BIST scheme for mixed-signal circuits
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
DC Built-In Self-Test for Linear Analog Circuits
IEEE Design & Test
Proceedings of the IEEE International Test Conference
A Statistical Sampler for a New On-Line Analog Test Method
Journal of Electronic Testing: Theory and Applications
An On-Chip Transfer Function Characterization System for Analog Built-in Testing
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Electrical characterization of analogue and RF integrated circuits by thermal measurements
Microelectronics Journal
A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing
Journal of Electronic Testing: Theory and Applications
Practical implementation of a network analyzer for analog BIST applications
Proceedings of the conference on Design, automation and test in Europe
A Built-in-Self-Test Σ-Δ ADC Prototype
Journal of Electronic Testing: Theory and Applications
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits
Journal of Electronic Testing: Theory and Applications
A low-power digitally-programmable variable gain amplifier in 65 nm CMOS
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A BIST Solution for Frequency Domain Characterization of Analog Circuits
Journal of Electronic Testing: Theory and Applications
Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications
Journal of Electronic Testing: Theory and Applications
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This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with a switched capacitor bandpass filter. A general methodology for the use of this structure in the functional verification of a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standard CMOS 0.5 驴m technology are presented to demonstrate the feasibility of the proposed BIT technique.