Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits
ATS '04 Proceedings of the 13th Asian Test Symposium
A Built-in-Self-Test Σ-Δ ADC Prototype
Journal of Electronic Testing: Theory and Applications
Linearity analysis in pipeline A-D converters
International Journal of Circuit Theory and Applications
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Testing analog and mixed-signal integrated circuits using oscillation-test method
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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An off-line reconfiguration method is proposed for pipelined ADCs to improve their fabrication yield. Some nonlinearities generated by op amps in pipelined ADC stages depend on their bandwidth, while their equivalent input-referred errors depend on the stage position. From these premises, the method is conceived as a two steps process. During the first step, an alternate-test based technique determines the best stage, from the bandwidth point of view, as the front-end stage. In the second step, analog residue path interconnections and a stage scaling are configured according to the results from the first step. This method has been verified for a 10-bits ADC, designed in a 65 nm CMOS technology, by means of Monte Carlo simulations, with promising results.