DSP-Based Testing of Analog and Mixed-Signal Circuits
DSP-Based Testing of Analog and Mixed-Signal Circuits
Analog Signal Generation for Built-in-Self-Test of Mixed-Signal Integrated Circuits
Analog Signal Generation for Built-in-Self-Test of Mixed-Signal Integrated Circuits
A Signature Analyzer for Analog and Mixed-signal Circuits
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Proceedings of the IEEE International Test Conference
HABIST: Histogram-Based Analog Built-In Self-Test
Proceedings of the IEEE International Test Conference
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Proceedings of the IEEE International Test Conference
A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Efficient and accurate testing of analog-to-digital converters using oscillation-test method
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Built-in self-test methodology for A/D converters
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An ADC-BiST scheme using sequential code analysis
Proceedings of the conference on Design, automation and test in Europe
An on-chip solution for static ADC test and measurement
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A digitally testable Σ-Δ modulator using the decorrelating design-for-digital-testability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Output Response Analyzer Circuit for ADC Built-in Self-Test
Journal of Electronic Testing: Theory and Applications
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This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.