Freeze!: a new approach for testing sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Putting the Squeeze on Test Sequences
Proceedings of the IEEE International Test Conference
Dynamic test compaction for synchronous sequential circuits using static compaction techniques
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Methods for Dynamic Test Vector compaction in Sequential Test Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Dynamic test Sequence compaction for Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
At-Speed Logic BIST Using a Frozen Clock Testing Strategy
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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