Bottleneck removal algorithm for dynamic compaction in sequential circuits

• Authors: S. T. Chakradhar;A. Raghunathan
• Venue: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• Year: 2006

We present a dynamic algorithm for test sequence compaction and test application time (TAT) reduction in combinational and sequential circuits. Several dynamic test compaction algorithms for combinational circuits have been proposed. However, few dynamic methods have been reported in the literature for sequential circuits. Our algorithm is based on two key ideas: (1) at any point during the test generation process, we identify bottlenecks that prevent vector compaction and TAT reduction for test sequences generated thus far, and (2) future test sequences are generated with an aim to eliminate bottlenecks of earlier generated test sequences. If all bottlenecks of a test sequence are eliminated, the sequence is dropped from the test set. Our algorithm can also target TAT reduction under the recently proposed partial scan-in/scan-out model by identifying and eliminating scan bottlenecks. If only the scan bottlenecks of a test sequence are eliminated, the test sequence can be trimmed to reduce the scan-in/scan-out cycles required to apply the sequence. For sequential circuits, we propose a sliding anchor frame technique to specify the unspecified inputs in a test sequence. The anchor frame is the first frame processed by a sequential test generator that is based on an iterative array model of the circuit, and the vector corresponding to the anchor frame is called the anchor vector. Under the sliding anchor frame technique, every vector in the test sequence being extended is considered as an anchor vector. This has the same effect as allowing observation of fault effects at every vector in the sequence, leading to a higher quality of compaction. The final test set generated by our algorithm cannot be further compacted using many known static vector compaction or TAT reduction techniques. For example, reverse or any other order of fault simulation, along with any specification of unspecified values in test sequences, cannot further reduce the number of vectors or TAT. Experimental results on combinational and sequential benchmark circuits, and large production VLSI circuits are reported to demonstrate the effectiveness of our approach