Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hybrid Fault Simulation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Initializability analysis of synchronous sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Journal of Electronic Testing: Theory and Applications
8.2 On Synchronizing Sequences and Test Sequence Partitioning
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
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We present a tool to compute a synchronizing sequence for synchronous sequential circuits. It consists of three parts. One part is an OBDD-based approach combined with a heuristic algorithm for preventing a memory overflow. This approach potentially finds a minimum length reset sequence. The second part is an improved three-valued based greedy algorithm. Its synchronizing sequence is not minimal in all cases, but experiments show that it is actually very good. The third part of the tool (and the focus of this paper) is a routine to quickly decide the non-resetability of a design. In contrast to previous approaches this routine is based on sufficient functional conditions to prove the non-resetability of certain memory elements. For the first time results about the resetability of the largest ISCAS'89 benchmark circuits are presented.