Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Symbolic fault simulation for sequential circuits and the multiple observation time test strategy
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fault simulation under the multiple observation time approach using backward implications
DAC '97 Proceedings of the 34th annual Design Automation Conference
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
A Hybrid Fault Simulator for Synchronous Sequential Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Full-Symbolic ATPG for Large Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
On the Initialization of Sequential Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Advanced Techniques for GA-based sequential ATPGs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
On the (non-)resetability of synchronous sequential circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Journal of Electronic Testing: Theory and Applications
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We present a fault simulator for synchronous sequentialcircuits that combines the efficiency of three-valued logicsimulation with the exactness of a symbolic approach. The simulatoris hybrid in the sense that three different modes ofoperation—three-valued, symbolic and mixed—are supported. Wedemonstrate how an automatic switching between the modes depending onthe computational resources and the properties of the circuit undertest can be realized, thus trading off time/space for accuracy of thecomputation. Furthermore, besides the usual Single Observation TimeTest Strategy (SOT) for the evaluation of the fault coverage, thesimulator supports evaluation according to the more general MultipleObservation Time Test Strategy (MOT). Numerous experiments are givento demonstrate the feasibility and efficiency of our approach. Inparticular, it is shown that, at the expense of a reasonable timepenalty, the exactness of the fault coverage computation can beimproved even for the largest benchmark functions.