SPIN-TEST: automatic test pattern generation for speed-independent circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SPIN-PAC: test compaction for speed-independent circuits
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Testing delay faults in asynchronous handshake circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Initialization-based test pattern generation for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft-error tolerance and mitigation in asynchronous burst-mode circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present SPIN-SIM, a logic and fault simulator for Speed-Independent Circuits, that extends the classical Eichelberger's method and overcomes its limitations. In order to improve simulation accuracy, SPIN-SIM adopts a 13- valued algebra, maintains the relative order of causal signal transitions, and unfolds time frames judiciously. In addition, complex gates are handled through replacement by pseudo-gate equivalents with regards to functionality, timing and faulty behavior. Experimental results show that SPIN-SIM incurs a negligible increase in computational time over Eichelberger's method, yet is much more accurate and achieves a significant improvement in fault coverage.