A new high-speed interconnect crosstalk fault model and compression for test space

Authors:
Shang Yuling;Li Yushan
Affiliations:
CAD Institute, Xi Dian University, Xi'an, China and School of Electronic Engineering, Guilin University of Electronic Technology, Guilin, China;CAD Institute, Xi Dian University, Xi'an, China
Venue:
WSEAS TRANSACTIONS on COMMUNICATIONS
Year:
2008

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Abstract

Signal integrity of high-speed interconnects has significant adverse effect on the proper function and performance of VLSI. A new crosstalk fault model is presented for testing glitch and delay in this paper. This model takes odd and even mode transmission into account based on parasitic RLC elements of interconnect. It can stimulate the maximal signal integrity loss compared to maximal aggressor (MA) model and maximal dominant signal integrity (MDSI) model. Then a compression algorithm for test space is proposed. Several properties such as symmetry, decay and superimposition are studied. Compression steps are explained in detail. Finally simulation is performed and experimental results show that this model is more effective than MA and MDSI models.