Signal integrity fault analysis using reduced-order modeling
Proceedings of the 39th annual Design Automation Conference
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs
Journal of Electronic Testing: Theory and Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A new high-speed interconnect crosstalk fault model and compression for test space
WSEAS TRANSACTIONS on COMMUNICATIONS
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test pattern generation for crosstalk fault of high-speed interconnect
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
Built-in sensor for signal integrity faults in digital interconnect signals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
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In this paper,we present a test pattern eneration algorithm aimin at signal integrity faults on long interconnects. This is achieved by considerin the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction methodology is employed. This strategy significantly improves the simulation time with slight loss of accuracy.